Circuit with built-in test and method thereof
US5790562A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 6, 1996 |
| Grant date | Aug 4, 1998 |
| Priority date | — |
| Expiry date | May 6, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/27
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit with a built-in self test, comprising: a circuit to be tested; a generating circuit coupled to the circuit to be tested, wherein the generating circuit generates (i) a series of input signals to the circuit to be tested and (ii) a series of reference signals; a space compaction circuit coupled to an output of the circuit to be tested, wherein the space compaction circuit uses a categorized response of the circuit to be tested to compact the output of the circuit to be tested by a maximum ratio and produces a series of output signals when the input signals are applied to the circuit to be tested; an analysis circuit coupled to the space compaction circuit and the generating circuit, providing a signal indicative of error in the circuit to be tested when the output signals fail to correspond to the reference signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.