Self test of core with unpredictable latency
US5790563A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 23, 1997 |
| Grant date | Aug 4, 1998 |
| Priority date | — |
| Expiry date | Jun 23, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31813
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A test method and means for in integrated circuit (10) having asynchronous communication capabilities including a transmitter (12) and a receiver (14). A pattern generator (24) is provided for generating patterns directly from within the integrated circuit (10). In the best presently known embodiment, a serializer (16) provides a serial output (20) and a deserializer (18) processes a serial input (22) into a parallel signal and provides the parallel signal to a receiver (14). The pattern generator (24) is preprogrammed to provide a parallel data pattern which can optionally and intermittently be provided to the transmitter (12) in a test mode (44). In the test mode (44), signal is routed from the serializer (16) directly to the deserializer (18) via an external loop back path (34) or an internal alternative loop back path (34a). When in the test mode, comparison unit (38) internally generates a pattern identical to that produced by the pattern generator (24) and locks onto signal received from the receiver (14) to perform a functional test (54) and an optional parametric test (58).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.