Parallel processing spacecraft communication system
US5790567A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 28, 1995 |
| Grant date | Aug 4, 1998 |
| Priority date | — |
| Expiry date | Aug 28, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2007/045
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An uplink controlling assembly speeds data processing using a special parallel codeblock technique. A correct start sequence initiates processing of a frame. Two possible start sequences can be used; and the one which is used determines whether data polarity is inverted or non-inverted. Processing continues until uncorrectable errors are found. The frame ends by intentionally sending a block with an uncorrectable error. Each of the codeblocks in the frame has a channel ID. Each channel ID can be separately processed in parallel. This obviates the problem of waiting for error correction processing. If that channel number is zero, however, it indicates that the frame of data represents a critical command only. That data is handled in a special way, independent of the software. Otherwise, the processed data further handled using special double buffering techniques to avoid problems from overrun. When overrun does occur, the system takes action to lose only the oldest data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.