Apparatus and method for synchronizing clock signals for digital links in a packet switching mode
US5790608A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 19, 1995 |
| Grant date | Aug 4, 1998 |
| Priority date | — |
| Expiry date | Dec 19, 2015 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S370/902
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
An apparatus and a method to synchronize the clock signal of a first (or slave) data terminal equipment A (240-1) to a second (or master) data terminal equipment B (240-2) connected to a communication network (10) through respectively a first network node (51) and a second network node (52). The communication network has a reference clock that it transmits to the second network node which compares it with the clock signal that it receives from the second data terminal equipment. The phase difference is then detected and converted into a frame which may be an ATM cell or any other frames so that it can be switched with the data frames sent by the second DTE and transmitted to the first DTE through the communication network. The frame containing the phase difference has a specific header so that it can be distinguished from the other transmitted data frames. The first network node receives the frames, detects the phase difference frame and decodes it before it is sent to a digital to analog converter. This later generates then an analog signal which adjusts the phase of the reference clock that the first network node has extracted from the communication network. The adjusted clock si…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.