Synchronized clock using a non-pullable reference oscillator
US5790614A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 2, 1996 |
| Grant date | Aug 4, 1998 |
| Priority date | — |
| Expiry date | Jul 2, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0334
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Digital signal processing techniques are used to synthesize a range of output frequencies locked to a non-pullable reference oscillator, and the synthesized output frequency is used in a slave low bandwidth phase-locked loop; by increasing digital resolution in a phase accumulation register, any desired resolution of output frequencies can be generated. The range of output frequencies is synthesized in such a way as to generate only high-frequency jitter, which can be easily filtered by follow-on, low-cost, relatively high bandwidth phase-locked loops which are typically needed for frequency multiplication in a given system. The magnitude of residual jitter is easily controlled by proper choice of the non-pullable oscillator reference frequency, the output frequency range to be synthesized and various other digital factors, such as divider ratios. Improved noise performance is achieved while still maintaining a wide pulling range of the composite phase-locked loop.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.