Processing system with simultaneous utilization of multiple clock signals
US5790842A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 11, 1996 |
| Grant date | Aug 4, 1998 |
| Priority date | — |
| Expiry date | Oct 11, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N21/4435
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for use in a set top box processing system to permit simultaneous utilization of two system clocks in applications in which certain processing system elements utilize one system clock operating at a non-integer multiple of another system clock used by other processing system elements. A synchronous phase detector is used to generate a clock enable signal suitable for use in a pipeline structure to facilitate data transfer between the different elements of the processing system. The clock enable signal includes phase information extracted from the first and second clock signals, and is suitable for use in driving one or more multiplexers in a pipeline structure or other state-based logic device to thereby allow data transfer between an element of the processing system operating at the first clock rate and an element operating at the second clock rate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.