Information processing apparatus for reducing power consumption by minimizing hamming distance between consecutive instruction
US5790874A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 29, 1995 |
| Grant date | Aug 4, 1998 |
| Priority date | — |
| Expiry date | Sep 29, 2015 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An instruction sequence optimization apparatus optimizes programs used in an information processing system that includes a program memory for storing programs, and a processing unit for fetching the programs from the program memory via an instruction bus. The apparatus includes an instruction sequence analyzing unit for analyzing mutual dependence relations between respective instructions constituting the program, and an instruction sequence modifying unit for modifying sequences of the instructions insofar as the mutual dependence relations analyzed by the instruction sequence analyzing unit are not influenced, to thus reduce Hamming distances between bit sequences appearing on the instruction bus when the instructions are transferred from the program memory to the processing unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.