Pipelined-systolic single-instruction stream multiple-data stream (SIMD) array processing with broadcasting control, and method of operating same
US5790879A · kind A · utility
Inventor
Key dates
| Filing date | Nov 17, 1995 |
| Grant date | Aug 4, 1998 |
| Priority date | — |
| Expiry date | Nov 17, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/8007
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A pipelined-systolic SIMD array processing architecture includes an array of processing elements, registers-delays, and multiplexers. One or more of the registers-delays having one or more registers are added to the input and output ends of the processing elements for transferring data, with broadcasting and systolic methods being combined to transfer data into and out of the processing elements. By utilizing a single control unit, the functionalities of computation, shifting, transferring and accessing, achieving faster speed in data processing and accessing, and switching circuits may be added between the input/output ends of the processing elements and the registers-delay arrays, so as to transfer data even faster.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.