High voltage, vertical-trench semiconductor device
US5793063A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 29, 1996 |
| Grant date | Aug 11, 1998 |
| Priority date | — |
| Expiry date | Mar 29, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An optically-triggered silicon controlled rectifier (SCR) (21) having a number of semiconductor layers (23, 24, 31) diffused into an N type substrate (22). Specifically, the SCR is formed by diffusing a first P+ layer (23) into an upper surface of the substrate. Then, an N+ layer (24) is diffused into a portion of an upper surface of the first P+ layer. An oxide layer (25) which is permeable to optical radiation is formed on the first P+ layer. A conductive cathode terminal (26) is then deposited on the N+ layer. Therefore, a trench (30) is etched in the lower surface of the substrate. The trench is defined by a depth and a surface. A second P+ layer (31) is diffused into the surface of the trench. The depth of the trench substantially defines a spacing between the first and second P+ layers. The chip is soldered onto a pedestal (33) formed on a lead frame (34). The solder is deposited in the trench and contacts the second P+ layer to form an anode terminal (36). The pedestal may be formed by either etching or stamping a depression (35) in the lead frame.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.