Reduction of trapping effects in charge transfer devices
US5793070A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 24, 1996 |
| Grant date | Aug 11, 1998 |
| Priority date | — |
| Expiry date | Apr 24, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/335
Abstract
A charge transfer device including a semiconductor substrate, a gate electrode provided in association with the substrate, the gate electrode having a corresponding channel region through which charge is propagated, the channel region having a predetermined potential; and means associated with the channel region for reducing charge trapping and recombination effects. In one aspect of the present invention, the reducing means includes a potential pocket defined within the channel region having a greater potential than the predetermined potential of said channel region. The potential pocket has a width dimension which is less than the corresponding width dimension of the channel region. The potential pocket is positioned in the center of the gate electrode, and is positioned so as to be aligned with a front edge of the gate electrode. The potential pocket is formed by an ion implantation into the semiconductor substrate, a region of an insulating layer having a thickness which differs from the thickness of the remainder of the insulating layer positioned between the gate electrode and the substrate, a second gate electrode positioned adjacent the first gate electrode, or a lightly or…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.