High density two port memory cell
US5793669A · kind A · utility
8Cited by
2References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 26, 1996 |
| Grant date | Aug 11, 1998 |
| Priority date | — |
| Expiry date | Jul 26, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A gate array structure includes a plurality of transistors (21-47) interconnected to form a two-bit memory cell. First and second interconnected transistors of the plurality are respectively provided in adjacent base sites (51, 53) of the gate array structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.