Bist jitter tolerance measurement technique
US5793822A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 16, 1995 |
| Grant date | Aug 11, 1998 |
| Priority date | — |
| Expiry date | Oct 16, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/033
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A circuit in a semiconductor device for testing jitter tolerance of a receiver in the semiconductor device. The circuit includes a jitter injection circuit that has an output connected to an input in a phase-locked loop circuit. The jitter injection circuit generates an output signal in response to an application of an input signal. The phase-locked loop circuit has an output that generates a clock signal, wherein the clock signal may be altered by the output signal from the jitter injection circuit. The clock signal from the phase-locked loop circuit controls transmission of data at the transmitter. Alteration of the clock signal caused by the jitter injection circuit alters the manner in which the transmitter transmits data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.