Synchronization circuit that captures and phases an external signal
US5793823A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Mar 17, 1995 |
| Grant date | Aug 11, 1998 |
| Priority date | — |
| Expiry date | Mar 17, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0008
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
It is an object to realize a synchronization circuit with small size and low consumption power which enables capturing and phasing of external data without running external clock in parallel. Internal clock (2) is delayed by a delay line (1) to produce delay clocks (3), and one of the delay clocks (3) having its rise almost corresponding to that of an external data signal (6) becomes a select clock (5). An elastic store circuit (7) is a circuit which controls a row of D-latches with a row of C elements. Thus the elastic store circuit (7) captures the external data signal (6) with enough set up hold time at timing of the select clock (5) and then outputs the captured external data as an internal data signal (8) in synchronization with the internal clock (2).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.