Digital phase locked loop having adaptive bandwidth for pulse stuffing synchronized digital communication system
US5793824A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 30, 1996 |
| Grant date | Aug 11, 1998 |
| Priority date | — |
| Expiry date | Apr 30, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J3/076
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A bandwidth-adaptive digital phase locked loop-based clock control arrangement controls the generation of a read-out clock used for retiming digital data signal interfaced with a synchronous data channel of a communication system, in which pulse-stuffing synchronization is employed to maintain clock synchronization of the digital data signal that is not bit-synchronous with a synchronous digital data channel over which the digital data signal is transported. The bandwidth-adaptive digital phase locked loop includes a loop filter to which the error signal is applied and a phase accumulator, coupled to the output of the loop filter and being operative to stepwise adjust the read-out clock signal. The loop filter has a first scaled path that includes a first, controllably stepped gain stage, and a second scaled path that includes a second, controllably stepped gain stage coupled to a frequency accumulator. The output of the frequency accumulator and the first stepped gain stage are summed and coupled to the phase accumulator. The gain of each of the first and second gain stages is incrementally adjusted in accordance with the magnitude of the error signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.