Synchronous event posting by a high throughput bus
US5793994A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 31, 1996 |
| Grant date | Aug 11, 1998 |
| Priority date | — |
| Expiry date | Jan 31, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4234
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A bus protocol technique removes the transaction used for posting indications of events to the host processor from the bus. The invention takes advantage of the fact that addresses typically on a high speed bus contain fewer bits than the entire bus width. Particularly, for a 32 bit bus, the 32 bit address space is not always necessary. The remaining bits on the bus are used for an encoded event tag. A bus transaction involves a first bus transfer which provides an address for writing or reading data, along with the event tag. The event tag is detected and decoded by the destination, and the event is posted to the processor which monitors and responds to events, in a manner which is synchronous with completion of the transaction. Thus, after the transaction on the bus, the message subject of the transaction is waiting in the memory, and notification of the event has occurred automatically and synchronously with completion of the transfer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.