Verification of strongly ordered memory accesses in a functional model of an out-of-order computer system
US5794012A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 9, 1996 |
| Grant date | Aug 11, 1998 |
| Priority date | — |
| Expiry date | Oct 9, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for detecting architectural violations of strongly ordered instructions by a computer architecture under test that supports out-of-order instruction execution is presented. A synchronizer concurrently controls the execution of an architectural model, which models high-level architectural requirements of the computer architecture under test and generates correct results under all received instruction test stimuli, and a behavioral model, which models the high-level architectural requirements of the computer architecture under test and executes instruction test stimuli according to the out-f-order instruction execution behavior defined by the computer architecture. The synchronizer matches all out-of-order instruction execution effects. The synchronizer verifies the correct handling of strongly ordered instruction by the computer architecture under test by keeping track of coherency check addresses from the bus emulator to the behavioral model, each memory request issued by the behavioral model to the bus emulator for any memory address other than the coherency check address, each respective move-in of a copy of each memory address, each access of each of the logg…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.