Data transfer apparatus fetching reception data at maximum margin of timing
US5794020A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 14, 1996 |
| Grant date | Aug 11, 1998 |
| Priority date | — |
| Expiry date | Jun 14, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0041
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A first variable delay circuit delays the reception data from the transmitting unit which is outputted from an input buffer and generates the delayed data to a data unidentifying time detecting portion. First and second latches have latch timings at regular intervals before and after a latch timing of a third latch for receiving and outputting by second and third variable delay circuits, respectively. In an adjusting operation, delay amounts of the second and third variable delay circuits are fixed to a value which is sufficiently smaller than a transfer period, a delay amount of the variable delay circuit is increased, a judging circuit detects a preceding edge of the reception data, subsequently, the delay amounts of the second and third variable delay circuits are sequentially increased while maintaining to the same value, and a following edge of the reception data is detected. In this instance, the timing of the third latch is set to the optimum point of the maximum margin. In a normal operation, the judging circuit detects a deviation from the optimum point and the delay amount of the first variable delay circuit is finely adjusted in accordance with the detection, thereby mai…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.