N-dimensional modified hypercube
US5794059A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 28, 1994 |
| Grant date | Aug 11, 1998 |
| Priority date | — |
| Expiry date | Jul 28, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/803
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A parallel array processor for massively parallel applications is formed with low power CMOS with DRAWM processing while incorporating processing elements on a single chip, with nodes connected in an n-dimensional modified non-binary hypercube. In a 4-dimensional modified non-binary hypercube embodiment, each node includes either processor memory elements on a single chip, each processor memory element having its own associated processing element, significant memory, and I/O, with each processor memory element supporting an external port. Pairs of ports are associated with each dimension, labeled X, Y, W, and Z. Eight nodes are connected in the X dimension to form a ring. Corresponding nodes from eight such rings are connected into rings in the Y dimension to form an 8.times.8 array of nodes, referred to as a cluster. Corresponding nodes of eight clusters are connected into ring (64 rings) in the Z dimension, forming an 8.times.8.times.8 array of nodes referred to as a "cluster ring". Corresponding nodes of eight cluster rings are connected into rings in the W dimension.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.