Low cost, highly parallel memory tester
US5794175A · kind A · utility
94Cited by
10References
17Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Sep 9, 1997 |
| Grant date | Aug 11, 1998 |
| Priority date | — |
| Expiry date | Sep 9, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/3191
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Automatic test equipment for semiconductor memories that provides testing of large arrays of semiconductor memory chips in parallel. Such massively parallel memory testing greatly enhances test throughput, thereby reducing cost. It greatly enhances the economics of testing memory device made according to a RAMBUS standard, which includes a low speed port and a medium speed port because it allows the same automatic test equipment to economically be used to test devices with the low speed port and the medium speed port.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.