Semiconductor memory using different concentration impurity diffused layers

US5796149A · kind A · utility

Assignee

• NIPPON STEEL CORPORATION · JP

Inventors

• Fumitaka Sugaya · Tokyo, JP
• Yasuo Sato · Kawasaki, JP

Key dates

• Filing date: Sep 8, 1995
• Grant date: Aug 18, 1998
• Expiry date: Sep 8, 2015

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/603

Abstract

A semiconductor memory which includes first and second memory cells, wherein the first memory cells include first MOS transistors each having impurity diffused layers provided inside of both of a source and a drain to expanding source and drain regions, the second memory cells include second or third MOS transistors each having an impurity diffused layer provided inside of one of a source and a drain or include fourth MOS transistors each having no impurity diffused layer provided inside of either thereof, as well as a method for fabricating the semiconductor memory. Differences in threshold voltage between the first and second to fourth MOS transistors are utilized as differences in storage status between the first and second memory cells so that data "0" or "1" is stored in each memory cell. There are also provided a semiconductor memory wherein differences between the first to fourth MOS transistors in the drain-source current flowing through the transistors when subjected to application of an identical gate voltage thereto are utilized to store four sorts of data in one memory cell, and provided a method for fabricating the semiconductor memory.