Latching mechanism for pulsed domino logic with inherent race margin and time borrowing
US5796282A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 12, 1996 |
| Grant date | Aug 18, 1998 |
| Priority date | — |
| Expiry date | Aug 12, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0963
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present invention provides a latching mechanism for use in high-speed domino logic pipestages. The latching mechanism allows time borrowing across latch boundaries, provides sufficient hold time for the output to be sensed by the next stage, and provides a circuit configuration in which race conditions related to the latching mechanism have inherent positive margin. The latching mechanism of the present invention is applicable to fully self-resetting domino logic, globally resetting domino logic, or any combination thereof. The latching mechanism is a set dominant latch having its set input driven by the output of the last domino logic gate in a pipestage, and having its reset input driven by the output of the last domino logic gate in a pipestage ANDed with a delayed version of the pulsed clock that triggers the domino chain of the pipestage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.