High-precision voltage dependent timing delay circuit

US5796284A · kind A · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Rainer Clemen · Böblingen, DE
• Wolfdieter Loehlein · Herrenberg, DE
• Harald Mielich · Stuttgart, DE

Key dates

• Filing date: Dec 16, 1996
• Grant date: Aug 18, 1998
• Expiry date: Dec 16, 2016

Classification

• Technology area (CPC H): Electricity
• CPC primary: H03K19/00323
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

For high-speed single-ended sensing of the small signal delivered from a (static) RAM or ROM cell, a voltage dependent timing delay circuit is disclosed which prevents early triggering of the set signal of the sense amplifier (SSA 66) when applying a high voltage screen test (i.e. 1.5 times V.sub.DD) to the cell. The timing of the SSA signal is achieved by a high precision delay chain comprising inverters, which is loaded by a voltage dependent current sink (70) coupled to the output of the chain. The inverter delay chain controls the input (SE0) for a driver for the SSA line (66). The current sink may be a pull down NFET (70) which is only activated when the supply voltage is above a determined switching threshold therefor. The gate voltage of the NFET is controlled by a bias control circuit (72) in such a manner that during operation at typical voltage levels, the NFET is deactivated, whereas at higher operating voltage levels (such as 1.5 * V.sub.DD) the NFET is turned on, thereby sinking current from the input (SE0) to the driver for the SSA line. The SSA signal is consequently delayed preventing the early triggering thereof.