Graphics accelerator having minimal logic multiplexer system for sharing a microprocessor
US5796288A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 15, 1996 |
| Grant date | Aug 18, 1998 |
| Priority date | — |
| Expiry date | Oct 15, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G5/39
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A minimal logic multiplexer system using tri-state drivers with one-hot enabling lead, provides high-speed access to processor elements by any one of a plurality of control units. The multiplexer system is implemented in a manner that minimizes the circuit implementation, minimizes gate delay within the circuit implementation, and allows processing instructions to pass from a control unit to the processor elements by way of multiplexed control lines therebetween. The multiplexer system contains control unit gate groups that are enabled and disabled in parallel by a select lead. Each control unit gate group can be implemented internal to the respective control unit or external in a common intermediary multiplexer circuit location.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.