Scaleable refresh display controller
US5796391A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 24, 1996 |
| Grant date | Aug 18, 1998 |
| Priority date | — |
| Expiry date | Oct 24, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2330/021
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A display controller (112) reduces the power consumed in displaying a graphics image in a portable wireless communications device (100) when a graphics image is smaller than the size of the display (118). The number of rows and columns used to display the graphics image is counted by a decoder (108) which is a microcontroller used to operate the communications device (100). The decoder (108) provides the reduced row or column count to the display controller (112), which reduces the frequencies of clocks (PIXEL CLOCK, LINE PULSE, FRAME PULSE) used for timing data transfers to the display (118). Power is reduced by operating the display (118) at a lower frequency while acceptable frame refresh rates are maintained.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.