Multiply accumulate computation unit
US5796645A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 27, 1996 |
| Grant date | Aug 18, 1998 |
| Priority date | — |
| Expiry date | Aug 27, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/5338
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multiply/accumulate computation circuit is provided. The circuit will perform the multiplication of a first binary number that is a multiplicand and a second binary number that is a multiplier to produce a product. The product can be added or subtracted from a previous result. The product may be negated. The product may be multiplied by a factor of two. Or the product that is multiplied by the factor of two may be added or subtracted from the previous result. The multiplication is accomplished in a modified Radix 4 Booth's encoding and translation circuit to produce a set of partial products that are combined in a n operand adder to form a final result.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.