System and method for transmission rate control in a segmentation and reassembly (SAR) circuit under ATM protocol
US5796735A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 28, 1995 |
| Grant date | Aug 18, 1998 |
| Priority date | — |
| Expiry date | Aug 28, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2012/5681
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A segmentation and reassembly circuit under the ATM standard uses a transmit cell schedule table (TCST) to support real time transmission of ATM cells in multiple constant bit rate virtual channels. In one embodiment, null cells are intentionally scheduled in a TCST. Transmission of the scheduled null cells ("forced null cells") or non-time critical cells are skipped to compensate for delays in an ATM cell transmission schedule, e.g. delays due to a bus latency. During such latency, null cells are generated from a null cell generator and a negative credit counter is incremented for each ATM cell transmission time missed. When transmission of a forced null cell is skipped, the negative credit counter is decremented.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.