Method and apparatus for performing microcode paging during instruction execution in an instruction processor
US5796972A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 14, 1997 |
| Grant date | Aug 18, 1998 |
| Priority date | — |
| Expiry date | Jan 14, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30145
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Method and apparatus for performing microcode paging during instruction execution in an instruction processor. In a preferred embodiment an instruction processor is provided that includes both a microcode ROM and a microcode RAM. The microcode ROM stores the current release of the microcode for the computer system, and the microcode RAM stores microcode patch instructions. During instruction execution, the present invention selects between the output of the microcode ROM and the microcode RAM, depending on whether the instruction requires a patch microcode instruction. If the desired microcode patch instruction is not stored in the microcode RAM, the instruction processor is temporarily interrupted and the desired microcode patch instruction or a group of microcode patch instructions are written, or paged, into the microcode RAM.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.