Method and apparatus for peripheral device control by clients in plural memory addressing modes
US5797031A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 26, 1997 |
| Grant date | Aug 18, 1998 |
| Priority date | — |
| Expiry date | Aug 26, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/5016
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A digital data processor has a central processing unit (CPU) that operates in plural addressing modes and or more adapters for receiving peripheral devices, e.g., PCMCIA devices. A first peripheral device service subsystem that handles communications between peripheral devices coupled to the adapters and software clients executing on the CPU in a first addressing mode. A second peripheral device service subsystem that handles communications between peripheral devices coupled to the adapters and clients executing on the CPU in a second addressing mode. The first peripheral device subsystem includes a configuration management section that allocates digital data processor resources, e.g., memory space, input/output channels, direct memory access (DMA) channels and interrupt (IRQ) levels, used for communications between the peripheral devices and clients, regardless of whether those clients are executing in the first or second addressing modes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.