FRAM, FRAM card, and card system using the same
US5798964A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 23, 1995 |
| Grant date | Aug 25, 1998 |
| Priority date | — |
| Expiry date | Aug 23, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Circuitry within a ferroelectric memory prevents inversion of the polarization of ferroelectric memory cells caused by a power on reset signal to avoid corruption of data stored therein. A ferroelectric memory includes a memory cell array, a plurality of word lines commonly connected to the gates of the cell transistors in the same row, a plurality of plate lines commonly connected to the plates of the cell capacitors in the same row, a plurality of bit lines commonly connected to one end of the cell transistors in the same row, and a power on reset circuit for generating a power on reset signal of a predetermined level for a predetermined period of time after the power supply is turned on. An erroneous programming prevention circuit within the memory includes a plurality of switching transistors connected between all of the bit lines and plate lines and a plurality of nodes at a predetermined potential. The switching transistors are controlled by the power on reset signal so that they are on for a predetermined period of time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.