Data output buffer control circuit of a synchronous semiconductor memory device
US5798969A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 20, 1996 |
| Grant date | Aug 25, 1998 |
| Priority date | — |
| Expiry date | Dec 20, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1051
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of controlling the buffering of output data by synchronizing with an external system clock, including the steps of generating an internal clock pulse, transferring data from a chip to a pair of data output lines in response to the internal clock pulse, generating an output mode control signal in synchronism with the internal clock pulse, gating the output mode control signal from the first edge of the internal clock pulse to the first edge of the next internal clock pulse to produce an output control signal, and driving data output to an output pad in response to the output control signal is disclosed. A data output buffer control apparatus of a synchronous semiconductor memory device operating in synchronism with an externally applied system clock pulse is also disclosed, which apparatus has an internal clock pulse generator for generating an internal clock pulse in response to the system clock pulse, an output register for transmitting data from the inside of the chip to a pair of data output lines in synchronism with the first edge of the system clock pulse, an output mode control signal generator for generating a predetermined output mode control signal in synchronism …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.