Microprocessor circuits, systems, and methods passing intermediate instructions between a short forward conditional branch instruction and target instruction through pipeline, then suppressing results if branch taken
US5799180A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 30, 1996 |
| Grant date | Aug 25, 1998 |
| Priority date | — |
| Expiry date | Oct 30, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30072
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Circuits, systems, and methods relating to processor which processes a plurality of sequentially arranged instructions. In the method, one method step (10) receives into a processor pipeline an instruction from the plurality of sequentially arranged instructions. Another step (12) determines whether the received instruction comprises a short forward branch instruction. If the received instruction comprises a short forward branch instruction, the method (14) issues a detection signal and (16) issues a condition signal representing whether or not the condition of the short forward branch instruction is satisfied. Continuing, the method (18) receives into the processor pipeline a first group of instructions of the plurality of sequentially arranged instructions, where each is between the short forward branch instruction and the target instruction. Each such instruction passes fully through the processor pipeline and the method (26) suppresses its result in response to the detection signal if the condition signal represents that the condition of the short forward branch is satisfied.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.