Power failure responsive apparatus and method having a shadow dram, a flash ROM, an auxiliary battery, and a controller
US5799200A · kind A · utility
700Cited by
7References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 28, 1995 |
| Grant date | Aug 25, 1998 |
| Priority date | — |
| Expiry date | Sep 28, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1441
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Data in a system having dynamic random access memories (DRAM's) is preserved despite loss of the primary source of electrical power to that system. A Flash RAM and a small auxiliary power source are employed by a controller independent of the system to transfer the DRAM contents to the Flash RAM immediately upon loss of primary system power. The data is also automatically returned to the DRAM after return of primary power with special data signals or sequences being utilized in a multiple controller environment so as to award the complete data recovery function to the first controller to demand attention.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.