Non-blocking peripheral access architecture having a register configure to indicate a path selection for data transfer between a master, memory, and an I/O device
US5799207A · kind A · utility
90Cited by
20References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 28, 1995 |
| Grant date | Aug 25, 1998 |
| Priority date | — |
| Expiry date | Mar 28, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4027
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer system is disclosed which has a master, such as a processor, a memory, and I/O device, a first transfer path, which includes a bus, and a second transfer path, which includes a transfer interconnection. Transfers between the memory and the I/O device are effected via the first path while transfers between the processor and the I/O device are transferred via the second path. The disparate treatment between these two types of transfers reduces the likelihood that the transfer via the second path is delayed and thereby reduces the likelihood that the master is totally blocked from operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.