Semiconductor device having a polycide structure
US5801427A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 11, 1997 |
| Grant date | Sep 1, 1998 |
| Priority date | — |
| Expiry date | Jun 11, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/601
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a semiconductor device having a polycide structure located on a stepped portion, halation during formation of a resist pattern is prevented, and oxidation of an upper surface of a high-melting-point metal silicide layer is prevented during formation of an interlayer insulating film on the polycide structure. In this semiconductor device, an upper layer which is formed of one layer selected from the group consisting of an amorphous silicon layer, a polycrystalline silicon layer, a TiN layer and a TiW layer is formed on the high-melting-point metal silicide layer forming the polycide structure. This effectively suppresses reflection of light beams by the upper layer located at the stepped portion during exposure for forming the resist pattern on the upper layer. Thereby, formation of a notch at the resist pattern is prevented, and the resist pattern is accurately formed to have a designed pattern. The upper layer made of the amorphous silicon layer or polycrystalline silicon layer prevents formation of an oxide layer at an upper surface of the high-melting-point metal silicide layer due to oxydation by Oxygen carried to the inside of the CVD furnace from the outside during formati…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.