Test method for power integrated devices
US5801536A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 19, 1995 |
| Grant date | Sep 1, 1998 |
| Priority date | — |
| Expiry date | Dec 19, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/2853
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method of checking an integrity of an electric power connection between a contact pad of an integrated circuit and a corresponding contact pin in an electronic power device, wherein the electronic power device includes at least one final power stage powered from the respective discrete contact pad connected by means of the electric power connection to the respective contact pin. The method of checking is accomplished by providing a resistive connection between two contact pads of the electronic power device bringing the at least one final power stage, powered from the first contact pad, to a conduction state, measuring the potential difference between the two contact pins connected to the two contact pads, and comparing the potential difference with a predetermined nominal potential difference.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.