Serial analog-to-digital converter using successive comparisons
US5801657A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 5, 1997 |
| Grant date | Sep 1, 1998 |
| Priority date | — |
| Expiry date | Feb 5, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/46
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A method for simultaneously performing bit serial analog to digital conversion (ADC) for a potentially very large number of signals is described. The method is ideally suited for performing on chip ADC in area image sensors. In one embodiment, to achieve N-bit precision, the method employs a one-bit comparator per channel (or set of multiplexed channels) and an N-bit DAC. To achieve N bits of precision, 2.sup.N -1 comparisons are sequentially performed. Each comparison is performed by first setting the DAC output to the desired value and then simultaneously comparing each of the pixel values to that value. If a pixel value is greater than the DAC output value, its comparator outputs a one, otherwise it outputs a zero. By appropriately choosing the sequence of comparison values, the pixel values are sequentially generated. In another embodiment, the DAC is omitted and a continuous ramp signal is generated for comparison with the analog input.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.