Implicit tree-mapping technique
US5801957A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 1, 1995 |
| Grant date | Sep 1, 1998 |
| Priority date | — |
| Expiry date | Nov 1, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/327
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for translating a boolean function into a logic circuit using gates from a standard library is provided. The method includes the steps of translating the boolean function into a network comprising a plurality of sub-trees, where each of the sub-trees represents a portion of the function, and where each sub-tree includes a plurality of representations for that portion of the function. The plurality of representations are stored in an alterative logic diagram, which comprises a plurality of ugates. The ugates are data structures which define the inputs and the connectivity of the respective ugate in the sub-tree. The sub-tree is mapped to gates from the standard library by selecting the best sub-tree representation. Accordingly, an improved method of logic synthesis is provided that allows for the optimal representation to be provided by starting with a wider range of inputs to the mapping process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.