Four bit pre-fetch sDRAM column select architecture
US5802005A · kind A · utility
19Cited by
2References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 23, 1996 |
| Grant date | Sep 1, 1998 |
| Priority date | — |
| Expiry date | Sep 23, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4097
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A synchronous DRAM memory device has four banks B0, B1, B2 and B3 of memory cell arrays 302-332 arranged across the length of the substrate 300. Each received address causes column address generators to select four bits of data for each bit of data in a data word. Data sequence circuits convey the four selected data bits to data bit bond pads 334,336 on the substrate in timed and selected sequential or interleaved order.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.