Scalable high performance switch element for a shared memory packet or ATM cell switch fabric
US5802052A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 26, 1996 |
| Grant date | Sep 1, 1998 |
| Priority date | — |
| Expiry date | Jun 26, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04Q11/0478
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A scalable high performance ATM cell/packet switch (HiPAS) element for a shared memory switch fabric application. The switch element includes a PAC Bus (Packet/ATM Cell Bus) and the Switch Fabric Controller bus (SC Bus). The HiPAS switch element receives and transmits the ATM cells/packets through the PAC Bus. The PAC bus provides independent parallel datapaths for the receive port and transmit port. The PAC Bus provides a unique structural feature to the HiPAS switch element and allows expansion to the switch capacity in a manner similar to a bit-slice processor. Multiple number of HiPAS switch elements can be concatenated to expand the capacity. In the concatenated configuration, the datapaths of the receive port and transmit port are interleaved so that the interconnection remains point-to-point. As the result, all of the switch ports in the switch execute the cell transactions concurrently on the PAC bus. In addition, each switch fabric port has a dedicated serial ports to exchange status information between the switch fabric and the switch port adapter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.