Convolution decoder using the Viterbi algorithm
US5802115A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 23, 1996 |
| Grant date | Sep 1, 1998 |
| Priority date | — |
| Expiry date | Aug 23, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/23
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A convolution decoder includes, for each state S of a shift register receiving an initial signal, an add-compare-select circuit which provides a one-bit decision for selecting either one of states 2S or 2S+1 as a state preceding the current state S. A decoding element traces back the memory according to a path indicated by the decisions stored in the memory in order to restore the succession of states of the initial signal. Each calculation cell associated with a state S further includes means for establishing a complex R-bit decision comprising, by decreasing weight, the one-bit decision of the calculation cell and the R-1 most significant bits of the complex decision established by the cell associated with the selected state 2S or 2S+1.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.