Method and apparatus in a data processing system for using chip selects to perform a memory management function
US5802541A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 28, 1996 |
| Grant date | Sep 1, 1998 |
| Priority date | — |
| Expiry date | Feb 28, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing system (10) including a chip select circuit (40) which allows flexible attribute protection, and a method for providing a plurality of chip select signals in the data processing system are disclosed. Each of two or more decoders (42, 48) determines whether a bus cycle address is within a programmable region and matches one or more programmable attributes, and if so activates a corresponding match signal. A logical operation circuit (60) then selectively causes a chip select signal (72) to be activated in response to a logical operation performed on the match signals. In one embodiment, the logical operation circuit (60) may cause the chip select signal (72) to be activated if either of two match signals (47, 53) is activated, allowing for example the same region of memory to be accessed from two address spaces using the same chip select signal (72).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.