Method and system for reducing memory access latency by providing fine grain direct access to flash memory concurrent with a block transfer therefrom
US5802554A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 5, 1997 |
| Grant date | Sep 1, 1998 |
| Priority date | — |
| Expiry date | Mar 5, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/2022
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for reducing access latency to stable storage are described. A technique referred to as fault trickling is used to improve access latency to stable storage such as flash memory. In particular, data requests from a central processing unit are preferentially satisfied by a memory management unit providing access to a main memory. When the requested data does not reside in the main memory, however, the memory management unit satisfies the request by providing direct fine-grain access to the flash memory. In addition, concurrently with satisfying the data request directly from the flash memory, a block transfer is initiated from the flash memory to the main memory. Once the block transfer is completed, a memory map, such as an address translation table, is updated to indicate that the data now resides in the more convenient source of data--the main memory. Accordingly, subsequent data requests, for that or proximately located data, can be satisfied by accessing the main memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.