Efficient storage of data in computer system with multiple cache levels
US5802563A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 1, 1996 |
| Grant date | Sep 1, 1998 |
| Priority date | — |
| Expiry date | Jul 1, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/272
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Memory space in the lower-level cache (LLC) of a computer system is allocated in cache-line sized units, while memory space in the higher-level cache (HLC) of the computer system is allocated in page sized units; with each page including two or more cache lines. Accordingly, during the execution of a program, cache-line-sized components of a page-sized block of data are incrementally stored in the cache lines of the LLCs. Subsequently, the system determines that it is time to review the allocation of cache resources, i.e., between the LLC and the HLC. The review trigger may be external to the processor, e.g., a timer interrupting the processor on a periodic basis. Alternatively, the review trigger may be from the LLC or the HLC, e.g., when the LLC is full, or when usage of the HLC drops below a certain percentage. A review of the allocation involves identifying components associated with their respective blocks of data and determining if the number of cached components identified with the blocks exceed a threshold. If the threshold is exceeded for cached components associated with a particular block, space is allocated in the HLC for storing components from the block. This scheme a…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.