Method and apparatus for increasing processor performance
US5802564A · kind A · utility
2Cited by
12References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 8, 1996 |
| Grant date | Sep 1, 1998 |
| Priority date | — |
| Expiry date | Jul 8, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0897
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for reducing the number of cycles required to implement load instructions in a data processing system having a Central Processing Unit (CPU). The CPU includes a cache register file, indexed via the offset field of the load instruction, for retaining cache lines from previously executed load instructions. The cache register file is then used by subsequent instructions (e.g. load instructions) requiring the data previously loaded therein. Thus, reducing the cycles normally associated with retrieving the data from the cache for the subsequent instructions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.