Cache memory having a read-modify-write operation and simultaneous burst read and write operations and a method therefor
US5802586A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 27, 1995 |
| Grant date | Sep 1, 1998 |
| Priority date | — |
| Expiry date | Feb 27, 2015 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multiple-way, set associative cache memory (20) allows burst read and burst write operations to occur simultaneously on different columns within a memory block during a read-modify-write operation. This is accomplished by using a write column logic (47) and a read column logic (51) to delay write column decode signals by one clock cycle from the read column decode signals. When data is being burst into and out of the cache during the read-modify-write operation, the first read cycle from the cache array (40) occurs, and one clock cycle later, the first write cycle occurs. The first write cycle occurs during the same time interval as the second read cycle. This increases the speed of a read-modify-write operation, relaxes timing constraints on the read and write operations, while reducing the power consumption of the cache.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.