Method and apparatus for determining a desirable directory/data block ratio in a cache memory
US5802600A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 12, 1996 |
| Grant date | Sep 1, 1998 |
| Priority date | — |
| Expiry date | Nov 12, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/601
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing system dynamically balances allocation of storage areas in a shared coupling facility that is devoted to storage of directory entries and data blocks. Each directory entry includes information regarding the validity of a data block that is locally stored by one or more processor modules in the data processing system. The system includes a coupling facility having a cache memory wherein a first portion is allocated to storage of data blocks and a second portion is allocated to storage of directory entries. Each directory entry, associated with a data block, indicates the validity or invalidity of data contained in a copy of the data block maintained by a connected computer module in its local memory. Each computer module, upon requiring a first data block and determining that (i) the first data block is present in its local memory (i.e., a buffer "hit"), but (ii) is not marked valid and (iii) is not present in the coupling facility (i.e., a cache "miss"), accesses the first data block from a disk store, even though the first data block in its local memory may be valid. A memory allocation procedure controls the sizes of the first portion and second portion of the c…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.