Solder process for enhancing reliability of multilayer hybrid circuits
US5803343A · kind A · utility
9Cited by
8References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 30, 1995 |
| Grant date | Sep 8, 1998 |
| Priority date | — |
| Expiry date | Oct 30, 2015 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49155
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A thick film hybrid multilayer circuit characterized by circuit components that are electrically interconnected with a multilayer structure composed of multiple layers of conductors interlaid with layers of a dielectric material in order to achieve high component density. The circuit components of the hybrid circuit are bonded to the multilayer structure with a novel soldering technique employing multiple solder compositions, which reduces the occurrence of dielectric fatigue cracking from thermal cycling. As a result, the multilayer structure exhibits significantly enhanced thermal fatigue resistance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.