Process for forming a self-aligned raised source/drain MOS device and device therefrom
US5804846A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 28, 1996 |
| Grant date | Sep 8, 1998 |
| Priority date | — |
| Expiry date | May 28, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/017
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention is directed to a process for forming a self-aligned raised source/drain MOS device comprising a planarized metal layer, preferably tungsten, overlying a source, a drain, and a gate that is provided on both sides with an insulating spacer to electrically isolate it from the source and drain. The planarized tungsten layer comprises a first portion whose lower surface is in contact with a polysilicon layer of the gate. The lower surface of each of the second and third portions of the tungsten layer is in contact with the source and drain, respectively. The second and third portions are insulated from the first portion by the insulating spacers, and the upper surfaces of all the portions comprise a coplanar surface. Planarization of the deposited metal layer thus provides ohmic contact at substantially the same level to the source, drain, and gate. In a self-aligned raised source/drain MOS device formed by the process of the invention, the second and third portions of the planarized metal layer preferably extend laterally over the field oxide and are characterized by an upper:lower surface width ratio of from about 2:1 to 4:1.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.