Semiconductor memory device and manufacturing method thereof

US5804851A · kind A · utility

Assignee

• Kabushiki Kaisha Toshiba · JP

Inventors

• Mitsuhiro Noguchi · Yokohama, JP
• Masami Aoki · Hiratsuka, JP

Key dates

• Filing date: Mar 19, 1997
• Grant date: Sep 8, 1998
• Expiry date: Mar 19, 2017

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D1/665

Abstract

A semiconductor memory device comprises a semiconductor substrate having a plurality of trenches selectively formed thereon, a plurality of capacitors formed in the trenches, each of the capacitors formed of the substrate, a capacitor insulating film formed on a surface of each of the trenches, and a storage node buried in each of the trenches interposing the capacitor insulating film, a plurality of transistors, formed on the substrate, for forming memory cells in relation to the plurality of capacitors, each of the transistors having a gate electrode formed on the substrate interposing a gate insulating film and source and drain regions formed in the substrate on both sides of the gate electrode, a plurality of element isolation films formed on side surfaces of upper portions of the trenches to surround the circumference thereof, respectively, the element isolation films having adjacent ones of the isolation films selectively coupled to each other such that at least one of the transistors is electrically insulated from another one of the transistors, and a plurality of conductive members, each connecting one of the source and drain regions of each of the transistors to the storag…