Comparator circuit with hysteresis
US5804994A · kind A · utility
9Cited by
4References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 14, 1997 |
| Grant date | Sep 8, 1998 |
| Priority date | — |
| Expiry date | May 14, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/3565
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A comparator with hysteresis which has a bias current circuit, a differential input stage, and an output stage is disclosed. The differential input stage uses a parallel transistor and an enabling transistor connected in parallel to one of the differential pair transistors to create hysteresis. The parallel transistor and enabling transistor are used to generated an effective offset voltage which must be overcome for the comparator to switch states.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.